EE Journal: The Year in EDA, Energy Harvesting, and Dolphins Eating Fugu

a techfocus media publication January 2, 2014   Welcome to EE Journal 2014! We just wrapped up 2013, which was a record year for us in every way. The EEJournal.com worldwide audience grew from 230,000 to over 260,000 worldwide - fueled by an explosion in growth of our social media channels. In the social media sphere, our Facebook presence alone grew to over 160,000 followers for our EEJournal and FreshBytes pages. We are also big on Twitter, LinkedIn, and even Google+, so check us out in those venues as well. We are tremendously excited about the 2014 we have in store for you. For starters, check out our new YouTube channel where we post our latest Chalk Talk episodes, sponsored videos, and other engineering-related media that will help keep you informed, entertained, and up-to-date. Our editors have a powerful lineup of new feature articles headed your way, and Amelia has an exciting year of Fish Fry interviews, news, and fun lined up and ready to podcast. To kick off the year, Bryon Moyer gives us an overview of EDA for 2013 and ponders what might be ahead for one of engineering's most critical industries. Thanks again for reading EE Journal! Kevin Morris - Editor, EE Journal     Lost photos of Antarctic expedition uncovered (Today) This animatronic wall of books moves in time with library visitors (Today) Why do we blow out candles on birthday cakes? (Today) This pickup truck is made of ice and you can actually drive it (Today) Hubble telescope finds evidence of clouds on a distant planet (Today) Dolphins filmed chewing on poisonous pufferfish in an apparent effort to get high (Yesterday) A map of the 124 United States of America that could have been (Yesterday) Long-lost photos show Mt. St. Helens just before its devastating eruption (Yesterday) A kids' book where every character can be 3-D printed (31-Dec) Why we sing Auld Lang Syne on New Year's Eve (31-Dec) Scientists discover 54-year-old message in a bottle near Canadian glacier (31-Dec) "Mini-kidney" grown from stem cells (30-Dec) Man wins a Guinness World Record for largest video game collection with 10,607 games (30-Dec) Pupil reflections in photographs could help investigators solve crimes (30-Dec) Wisconsin is using cheese to thaw icy roads (30-Dec) Hundreds of radio-tagged sharks tweet warnings at Australian swimmers (27-Dec) Michaelangelo's illustrated grocery list (27-Dec) Carmat self-regulating artificial heart implanted in first human subject (27-Dec) 3D printer that draws pictures in jello shooters (26-Dec) Glass Microbiology, beautiful glass sculptures of deadly pathogens (26-Dec) Scientists grow liquid crystal "flowers" to use as lenses (26-Dec) A real-life memory-erasing technique for humans (24-Dec) Parisian graffiti block preserved in digital 3D ahead of demolition (24-Dec) Cube-shaped robot balances on one corner and can move on its own (24-Dec) Don't be scared of the vampire squid (23-Dec) With development cycles shrinking and software content growing, the demand for software-driven, in-context validation of new RTL blocks and IP requires that FPGA-based prototypes be delivered as fast as possible. The Synopsys HAPS Developer eXpress (HAPS-DX) provides best of class prototyping hardware and automation software tools in a package that is focused on rapid bring-up and accelerating the availability of ASIC RTL block and IP prototypes for design teams who need state-of-the-art prototyping solutions. Click here for more information Mysterious IR Array posted by Bryon Moyer Bosch has a new IR sensor array. Although… getting more info may be tough. (19-Dec) IntrinsicID and InsideSecure Come to DropBox posted by Bryon Moyer A once-obscure technology peeks through to everyday users. (18-Dec) A New Piezoelectric Oscillator posted by Bryon Moyer Sand 9 introduces a new device and family (17-Dec) Sorting Cells posted by Bryon Moyer In an early application of lens-free imaging, Imec sorts good from bad. (16-Dec) Automotive IMU posted by Bryon Moyer Bosch takes a Sensortec IMU into cars. What does that involve? (12-Dec) Next-Generation Image Signal Processor posted by Bryon Moyer Imagination Technologies announces Raptor architecture (11-Dec) January 02, 2014 Clarinox Bluetooth and Wi-Fi support for Texas Instrument WiLink™ 8Q and Green Hills Software's INTEGRITY® Real-Time Operating System January 01, 2014 PNI Sensor Introduces Highest-Performance Geomagnetic Sensor for Consumer Applications ITTIA Updates Software for Large Data Management on Embedded Devices December 27, 2013 3M Showcases 3M™Quantum Dot Enhancement Film Technology at CES 2014 Sidense 1T-OTP Memory Macros meet JEDEC Accelerated Testing Qualifications at Two TSMC 28nm Process Nodes December 20, 2013 connectBlue® to Participate in IoT Project for Home Cancer Care Mentor Graphics adds S1000D compliance and more with latest release of Capital software for vehicle electrical system design, manufacture and service. Vincotech Integrates Several Power Modules into One Silm 90° Housing Honeywell Launches High Sensitivity Latching Digital Hall-Effect Sensor Integrated Circuits Nordic Semiconductor announces Bluetooth Smart solution for Rezence Wireless Charging and the S120 8-link central role Bluetooth low energy SoftDevice for the nRF51822 IAR Systems further simplifies designing and testing of state machine-based embedded applications December 19, 2013 RAID-Capable Box PC from MEN Micro Offers Flexible Storage Capacity Spansion Dual-Quad Serial Flash Delivers Industry-Leading Performance for Graphic-Rich Applications GE Extends DLynx* Series with New Dual 12-Amp Point of Load Modules STMicroelectronics Joins ARM mbed Project Resettable Fuse from Diodes Incorporated Enhances System Reliability IAR Systems updates its popular development tools for Atmel AVR 8-bit microcontrollers Avnet Electronics Marketing Americas Looks to "Internet of Things" as a Top Technology Trend in 2014 Dual 3A, 4MHz, Synchronous Step-Down Regulators with DDR Memory Now Offered in High Reliability H Grade & Military MP Grade to +150°C Telit Unwraps First Positioning Module Based on MediaTek's Single Chip Multi-GNSS Receiver SoC Technology December 18, 2013 DTS-HD Decoder Now Available on Cadence Tensilica HiFi DSP Cores Microchip Announces New 5 GHz 50 ohm Matched WLAN Front End Module for IEEE 802.11a/n/ac Applications videantis joins Khronos, targets OpenVX™ computer vision API 40VIN, 2.1A Rail-to-Rail LDO+ Offers Extensive Monitoring, Protection & Cable Drop Compensation Mentor Graphics Acquires Oasys RealTime to Bring RTL Synthesis to its Digital Implementation Flow DVCon 2014 Announces Technical Program with Record Number of Tutorials & Poster Sessions Vector Software Releases VectorCAST 6.2 Embedded Software Testing Suite MyriadRF launches Zipper, open-source hardware interface board to Altera and Xilinx platforms World's Smallest CSP MEMS Oscillator from SiTime Paired with Mini GPS Receiver from Telit to Enable New Wave of Ultra-Miniature Tracking and Navigation Devices December 17, 2013 Coilcraft CPS Launches Testing & Validation Services ALi's Advanced Security STB Chipset Receives NOCS Certification from NAGRA Achronix Demonstrates Embedded 100G Ethernet in Speedster22i 22nm FPGAs     The Year in EDA Did Anything Happen? by Bryon Moyer 2013 is coming to a close, and this is usually a time for reflecting on what's happened in the past year and what's going to happen in the coming year. The thing is, though, when I sit back and reflect, well, I don't know; it just seems like 2013 was a quiet year for EDA. So I took a couple of approaches to reviewing the year. One is to see what the Big Guys did and the other was to solicit some other opinions as to what's in and what's out.  Read More   Wag the Cantilever Happy Energy Harvesting by Bryon Moyer   Out of the Fab and Into the Frying Pan Fryin' up Some Semis with Mike Gianfagna by Amelia Dalton   Europe Takes on the World by Dick Selwood   Rockin' It Industrial Style Fans of Heavy Metal Will Like TI's New Delfino MCU by Jim Turley   Articles Archive Maximize Your Power and Efficiency with PADS Interactive Placement and Routing Chalk Talk sponsored by Mentor Graphics A Significant Technology Advancement in High-Speed Link Modeling and Simulation White Paper sponsored by Altera Synopsys' HAPS Developer eXpress FPGA-based Prototyping Solution White Paper sponsored by Synopsys Faster Time to First Prototype White Paper sponsored by Synopsys Designing with Vivado IP Integrator Video sponsored by Xilinx How to Achieve 10X Faster Power Integrity Analysis and Signoff White Paper sponsored by Cadence Solutions for Mixed-Signal SoC Verification Using Real Number Models White Paper White Paper sponsored by Cadence Xilinx UltraScale Architecture for High-Performance, Smarter Systems White Paper sponsored by Xilinx Cadence Low Power Solution - RTL to GDSII Low Power Design Chalk Talk sponsored by Cadence Supercharging Design Performance and Productivity with Altera FPGAs and Best-in-Class IP White Paper sponsored by Altera Routing Interfaces Quickly & Efficiently on PCBs Chalk Talk sponsored by Cadence Overcome the Challenges of Highly Constrained Designs Chalk Talk sponsored by Mentor Graphics SmartFusion2 SoC FPGA Demo: Error Detection and Correction of eSRAM Memory User's Guide White Paper sponsored by Microsemi Cadence Tempus Timing Signoff Solution Chalk Talk sponsored by Cadence SmartFusion2 SoC FPGA PCIe Control Plane Demo User's Guide White Paper sponsored by Microsemi Building a New Type of IP Factory Chalk Talk sponsored by Cadence Battery Management Solutions Chalk Talk sponsored by Mouser 100G Ethernet Packet Parsing with Spacetime Chalk Talk sponsored by Tabula Enabling the Internet of Things: Introducing Atmel SAM D20 Cortex M0+ Family Chalk Talk sponsored by Atmel Advanced Smart Display Solutions Chalk Talk sponsored by GLOBALFOUNDRIES What is Design Security in a Mainstream SoC? Chalk Talk sponsored by Microsemi How to Design a Sigma Delta Mixer Circuit Chalk Talk sponsored by Triad It's the Software, Silly! - Success with FPGA-based Prototyping Chalk Talk sponsored by Cadence World's Smallest FPGAs Solve 4 Big Problems Chalk Talk sponsored by Lattice Market-Specific Custom IC Solutions Chalk Talk sponsored by GLOBALFOUNDRIES Enabling New Applications with NFC Connectivity and Energy Harvesting Chalk Talk sponsored by Mouser Introducing Digitally Enhanced Power Analog Chalk Talk sponsored by Mouser How To Save 99% on Your Next Mixed Signal ASIC Design (part 2 of a 3-part series) Chalk Talk sponsored by Triad DO-254 Requirements Traceability with Spec-TRACER Chalk Talk sponsored by Aldec Low-Power Estimation & Verification With ZeBu Chalk Talk sponsored by Synopsys How To Save 75% on Your Next ASIC Design Chalk Talk sponsored by Triad Timing Closure Made Easier with Stylus Chalk Talk sponsored by Tabula Solving the 100Gbps Challenge with ABAX2 Chalk Talk sponsored by Tabula High Speed Data Acquisition and Software Defined Radio Made Simple Chalk Talk sponsored by 4DSP The Hardware Prototype Arrives -- Find Design Errors Fast and Improve Design Quality Chalk Talk sponsored by Kozio Why Do I Need a Customizable ARM-based SoC? Chalk Talk sponsored by Altera Simplifying Industrial Ethernet Design Chalk Talk sponsored by Altera Powering Stratix V FPGAs (Made Easy) Chalk Talk sponsored by Linear Technology Maximizing Battery Life with TI's Wolverine Technology Chalk Talk sponsored by Mouser Verification Methodologies (Made Easy) Chalk Talk sponsored by Aldec   The Year in EDA (2 replies) In tandem with Forte's observations on SystemC for HLS and verification, design creation in ESL will come back around as a productivity gap (i.e., lack of it) from text-based editing will need to be addressed. posted by garydpdx on 12/26/13 at 3:35 PM     Mysterious IR Array (1 replies) It might have to do with government restrictions on devices that can be used for targeting people - the Panasonic GridEYE is considered a "controlled device" here in the USA. I was going to do a product based on it (i.e. it can tell you how many people ar… posted by moxbox on 12/21/13 at 10:55 AM     Out of the Fab and Into the Frying Pan (1 replies) What do you think about my interview with Mike Gianfagna? Where do you think the semiconductor industry is headed next year? posted by amelia on 12/20/13 at 9:43 AM     Europe Takes on the World (1 replies) Is a pan-governmental push going to turn the tide? Or is it going to be a case of lots of wet feet? posted by Dick Selwood on 12/19/13 at 1:30 PM     Imaging Without Lenses (1 replies) What else can you envision doing with lens-free imaging? posted by bmoyer on 12/17/13 at 10:00 AM           You're receiving this newsletter because you subscribed at our web site www.eejournal.com. If someone forwarded this newsletter to you and you'd like to receive your own free subscription, go to: www.eejournal.com/subscribe If at any time, you would like to unsubscribe, click here. (But we hope you don't.) If you have any questions or comments, send them to comments@eejournal.com. All material copyright © 2008- 2014 techfocus media, inc. All rights reserved. Privacy Statement

Sent to: jagadesh2020.fpga@blogger.com

Unsubscribe

Techfocus Media, Inc., 4620 W Burnside Rd, Portland, OR 97210, USA

Happy New year 2013!!!!

Introducing EE Journal's MEMS and Smart Systems Newsletter

As a subscriber to Electronic Engineering Journal's family of publications, we want to extend a special invitation for a free subscription to our new MEMS and Smart Systems Newsletter. 

I've heard enough. Sign me up now.

We've been covering this space for a while, but we haven't had a newsletter dedicated to it – and we decided the time is right; it's a hot topic.

Yep, I agree. Sign me up. 

We actually had a really hard time deciding what to call it. MEMS is a prominent and popular component of what this is about, but it's more than that. It's sensors of any kind, microfluidics, embedded vision, gesture recognition, touch technology. It's about what you can make out of these – all of the consumer, industrial, and medical devices that have the ability to evaluate and report their context and surroundings. Networks of sensors (both large-scale and even within a single system); the internet of things. Energy harvesting to power remote sensors; smart meters to power homes.

Wow! You're going to cover all that? Sign me up!

It's hard to encapsulate that all in a word or two. At the end of it all, we were left with "smart." That may mean different things to different people, but we refer to the fact that, not only can these systems tell that something's happening to or around them, they can make decisions – hopefully smart ones – and take action – hopefully smart action. 

The "smart" thing to do is to sign up now, isn't it?

There are fascinating technology stories and compelling end applications. It's multi-disciplinary, including electrical, mechanical, chemical, and biological technology; digital, analog, power, wireless, semiconductor, EDA, software. Lots going on and lots to learn. Perfect for all you Renaissance men and women.

That's me! Sign me up!

We think you'll enjoy our coverage of an area that is going to affect more and more of your systems as time goes on. As we have before, we'll focus on bringing technology, insight, and an occasional opinion or four. 

Here goes!

Sent to: jagadesh2020.fpga@blogger.com

Unsubscribe

Techfocus Media, Inc.
4620 W. Burnside Road
Portland, OR 97201
USA

Happy Independence Day 2012

We remembers Steve Jobs

Apple has lost a visionary and creative genius, and the world has lost an  

amazing human being

Journal on Demand - June 2, 2011

Industry's First 28-nm High-End FPGA Running at 14.1 Gbps Get an initial look at the industry's first 28-nm high-end FPGA. In our Stratix® V FPGAs, you'll get devices featuring: An industry-record 3.9 billion transistors, One million logic elements, Integrated transceivers with data rates up to 28 Gbps and an abundance of hard intellectual property (IP) blocks. Samples are shipping now. Watch this 3-minute video to see the progress of our silicon checkout process, as well as 14.1-Gbps transceiver performance. (Altera) Optimize Power and Cost with Altera's Diversified 28-nm Device Portfolio Altera's 28-nm devices provide a diversified product portfolio tailored to support a broad spectrum of applications, ranging from low cost and power, to high-end applications. This white paper describes the power and cost advantages of Altera's Stratix® V, Cyclone® V, Arria® V, and HardCopy® V devices. (Altera) Intel Atom™ Processor with built-in Altera Arria® FPGA In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package. (Arrow) Parameterizable Content-Addressable Memory This application note describes a parameterizable content-addressable memory (CAM), and is accompanied by a reference design that replaces the CAM core previously delivered through the CORE Generator™ software. The CAM reference design should be used for all new FPGA designs targeting Virtex®-6, Virtex-5, Virtex-4, Spartan®-6, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP FPGAs, and newer architectures. All the features and interfaces included in the reference design are backward compatible with the LogiCORE™ IP CAM v6.1 core. In addition, because the reference design is provided in plain-text VHDL format, the implementation of the function is fully visible, allowing for easy debug and modification of the code. (Xilinx) True Wireless Broadband Mark Quartermain of Xilinx explains how the next generation of 4G digital cellular standards, Long Term Evolution, represents a significant step forward for wireless operators...and more! (Xilinx) Secure Foundations In a world where attacks on electronic systems can be conducted remotely, security is a vital component of system design. Even systems that do not have to store personal or commercially confidential data now have to be designed with security in mind to prevent their core intellectual property (IP) from being copied and reused illegally. In these examples, we can see the two elements of electronic system security: design security and data security. Increasingly, the two depend on each other. (Microsemi) Single-Event Effect Mitigation in RTAX-DSP Space-Flight FPGAs When high-energy ions present in space strike the substrate of an IC, their impact can cause momentary current/voltage pulses in the IC's circuitry. When these pulses are sufficient to change the data on the circuit, they are referred to collectively as single-event effects (SEEs). (Microsemi) Effectively Testing The Display Pixel Interface (DPI) This is part two of a multi-part white paper series on effectively testing embedded display systems. This function requires a clear understanding of the various interfaces which may exist in the system, and the detailed challenges in testing and debugging them. This paper describes a number of specific techniques for testing a parallel Display Pixel Interface (DPI), which is both the most common and the most physically complex display interconnection (Kozio) Display System Testing Demonstration Embedded processors are becoming dramatically more sophisticated, and in many cases that sophistication includes a variety of user interface devices. View this video to see how the kDiagnostics environment has been enhanced to support these user interfaces. (Kozio) Adding Wi-Fi to Your FPGA Design In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system. (Altium) Teradici Success Story Synopsys and Teradici: ASIC Prototyping Made Fast and Efficient with Synplify Premier (Synopsys) Team Design For Large FPGA Projects Are your FPGA projects getting big enough that you need help? Team design for FPGAs can be a confusing process if you don't have the right tools and infrastructure in place. Join Amelia Dalton as she chats with Jeff Garrison from Synopsys about the unique challenges facing design teams as they take advantage of the incredible power of today's huge FPGAs. (Synopsys) FPGA Design Methods for Fast Turnaround This paper takes an in depth look at a variety of techniques to help you speed up your synthesis iterations. Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations. (Synopsys) Power Considerations In FPGA Design Power has always been a design consideration. Traditionally, though, a lower priority has been assigned to power than to most other variables (speed/performance, cost, time-to-market, risk, etc.). In today's marketplace, however, power has become a very important component in the designer's decision making process. There is good reason for this. Power translates to significant system cost. (Lattice) Implementing High-Speed DDR3 Memory Controllers in a Mid-Range FPGA Implementing a high-speed, high-efficiency DDR3 memory controller in a FPGA is a formidable task. Until recently, only a few high-end (read: expensive) FPGAs supported the building blocks needed to interface reliably to high speed DDR3 memory devices. However, a new generation of mid-range FPGAs now provides the building blocks, a high-speed FPGA fabric, clock management resources and the I/O structures needed to implement the next generation DDR3 memory controllers. (Lattice) Processor IP Checklist With their associated software-development tools, simulation models, and EDA flow scripts, processor and DSP IP blocks affect more than just the hardware design; their influence permeates the entire SOC design project. Here is a list of questions to ask yourself, your team, and any processor IP providers you contact. This list will help you to avoid unhappy IP choices and will help you get exactly what your team needs to develop successful SOC designs on time, within budget, and with minimal hassle. (Tensilica) 10 Reasons to Customize a Processor Core There are plenty of really good, proven processor cores on the market today. But if you have more than simple control tasks, perhaps you've considered using a processor that you can customize. We'll give you 10 good reasons why you should consider customizing your core in your next SOC design. (Tensilica)