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Journal On Demand - April 7, 2010

a techfocus media publication :: January 6, 2010

Welcome to the April issue of our new monthly Journal On Demand newsletter.  This month, our popular new supplement to FPGA Journal, Embedded Technology Journal, and IC Design and Verification Journal brings you an exciting lineup of white papers, videos and webcasts from industry-leading vendors, as well as the newest episodes of our popular Chalk Talks with Amelia Dalton. If you have any questions or comments, please let us know - or better yet, jump right in and make yourself heard on our new, remodeled Journal Forums. Our community of over 100,000 engineers worldwide can probably answer just about any technical question you can come up with. Thanks for reading, Kevin Morris Editor-in-chief, Techfocus Media, Inc. Next Generation System Design – Platforms versus Tool-Chains (WHITE PAPER) This paper will enumerate the benefits of a platform-based system design approach. The original electronic design process built by linking tools together has remained largely unchanged for decades (i.e. tool-chains). A layered platform architecture unifies PCB, FPGA and embedded software development into one application. At the foundation is a unified data model that enables numerous data management benefits including versioning and ECO management. Companies switching to a platform based design process are doubling their productivity as compared to traditional tool-chains. (Altium) ______________________________________________________________________________ 16-bit Performance for an 8-bit Price: TI's MSP430 Microcontroller Value Line (PRODUCT BULLETIN) The ultra-low power MSP430™ microcontroller Value Line offers superior 16-bit MCU performance and industry leading ultra-low power consumption for cost sensitive applications that have traditionally depended on low cost 8-bit microcontrollers. Starting at 25 cents (in 100K volumes), the MSP430G2xx Value Series ensures 8-bit developers no longer need to sacrifice performance, power efficiency or scalability because of price. (Texas Instruments) ______________________________________________________________________________ Actel FPGAs for Handheld Portable Solutions (CHALK TALK) With the industry's lowest power and widest range of small packages, it's no wonder Actel IGLOO® FPGAs can be found in the latest handheld portable devices. Actel has been designed into a wide array of handheld devices, including smartphones, eBooks, cameras, medical devices, industrial scanners, military radios, and the list goes on. Actel IGLOO low power FPGAs bring reprogrammability, design security, integration, small form factor, and live-at-power-up operation to handheld portable applications. In this webcast host Amelia Dalton chats with Naseem Aslam about Actel solutions for handheld portable applications. (Actel) Design Made Easy With Mixed-Signal FPGAs and State of the Art Software Tools (WHITE PAPER) This paper examines the evolution path for FPGAs with embedded processors, and the design tools that support them, and considers whether engineers need to evolve their techniques to accommodate the integrated silicon or whether they can continue to manage their boundaries at the silicon level instead of the board level. New techniques are available in the embedded mixed‐signal FPGA design flow, but do they smooth the adoption of a fully integrated device? Find out by reading the White Paper. (Actel) Actel SmartFusion: Intelligent, Innovative Integration (WHITE PAPER) Actel SmartFusion™ Intelligent Mixed Signal FPGAs – Innovative, Intelligent, Integration. Introducing the only device that integrates a flash FPGA, hard ARM® Cortex™-M3-based microcontroller subsystem (MSS) and programmable analog into a complete, integrated solution. Don't compromise your embedded design. Build the system you want, with all the features you need, on a single-chip solution. Read the White Paper to learn more. (Actel) ______________________________________________________________________________ Xilinx Automotive Spartan-6 FPGA Devices (VIDEO) Learn more about how the new line of automotive devices from Xilinx® can help advance next generation driver assistance, driver information, and driver infotainment applications. Presented by Thorsten Kistler, Automotive Marketing Manager, Europe. (Xilinx) Spartan-6 FPGA Industrial Ethernet Kit (VIDEO) Accelerate your next generation factory automation design with the Spartan®-6 FPGA Industrial Ethernet Kit, jointly developed with Avnet. Walk through a demonstration of the benefits and features of the kit with Giulio Corradi, Senior System Architect (Xilinx) ______________________________________________________________________________ Streaming Multichannel Uncompressed Video in the Broadcast Environment (WHITE PAPER) Designing video equipment for streaming multiple uncompressed video signals is a new challenge, especially with the demand for high-definition video streams. This white paper examines how a multichannel streaming PCIe DMA controller and other "building block" IP cores are combined within a Cyclone IV GX FPGA to support SD- and HD-SDI applications using an open-source video packet streaming-format protocol such as those used in non-linear editors, video servers, and video-capture applications. (Altera) Easily Support WDR CMOS Image Sensor Processing with Low-Cost FPGAs (VIDEO) High-definition (HD) wide dynamic range (WDR) CMOS image sensors are ideal for applications like video surveillance cameras. And for the underlying technology, FPGAs are optimal because they deliver the high bandwidth these sensors demand. In this 7-minute video, you'll see how an FPGA-based platform easily performs complex image processing to support WDR CMOS image sensors. (Altera)

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IC Journal - March 30, 2010

a techfocus media publication :: March 30, 2010

From the Editor Technology programs come and go. Some are successful, some aren't. But the success of some businesses can be determined as much by business model or marketing programs as much as technology. And again, some are successful; some aren't. This week we take a look at one program, notable both for the tenacity of its champion and the staying power of its main protagonist. As yet, it wouldn't be considered notable for its success. Read ahead and see... In January it was Cliff. In February it was Ian. Now, there are just a few days left for YOU to be our March winner of a $500 Amazon.com gift certificate for the best posts on Journal Forums. Thanks as always for reading. We encourage you to share your thoughts in the new easier-to-use comments area right below the articles; don't be shy. Or you can get a lively discussion going on our new FORUMS. Bryon Moyer - Editor, IC Journal        EVENTS & ANNOUNCEMENTS Webinar: Complementing Emulation with Rapid Prototyping In this on-demand webcast Synopsys discusses how FPGA-based rapid prototyping is used as a natural complement to emulation when shortening development time is critical to ASIC and SoC projects. Together, these systems offer designers and verification engineers a highly powerful and productive solution for hardware debug, system integration, system validation and pre-silicon software development to reduce the risk of design re-spins, minimize schedule risk and meet demanding time-to-market needs. Click here to watch IC Journal Forum Competition Win 500 bucks just for being smart! LEMME AT THEM FORUMS! (Click here for competition details) On Demand Billion Gate Emulation with ZeBu-Server (CHALK TALK) Running out of verification capacity? Today's huge designs demand a new solution with dramatically improved speed, capacity, and flexibility. Join Amelia Dalton as she talks with Ron Choi of Eve about the challenges of Billion-Gate emulation. (EvE) Solving Today's Tough FPGA Design Problems (CHALK TALK) Are your FPGAs outgrowing your tool flow? Join Amelia Dalton as she talks with Jeff Garrison of Synopsys about setting up your design tools for today's more demanding FPGAs. (Synopsys) Introducing Synphony High Level Synthesis (CHALK TALK) Having difficulty getting complex algorithms into hardware? Join Amelia Dalton as she chats with Chris Eddington from Synopsys about the latest advances in high-level synthesis - going directly from Matlab into optimized hardware design. (Synopsys) Power Management in an Embedded Multiprocessor Cluster (WHITE PAPER) Coherent microprocessor clusters, having localized instruction and data caches per CPU, require special techniques to maintain consistency between localized cache contents and their common address region. For embedded systems, designers typically apply snoop-based schemes to maintain memory coherence. This scheme introduces ownership attributes of local cache lines, which are posted throughout the cluster upon intent to use or change. (MIPS) ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers (WHITE PAPER) Moore's law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically "break" existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools. (EvE) FPGA - PCB Co-Design Done The Right Way (CHALK TALK) Join Amelia Dalton as she talks with Hemant Shah of Cadence Design Systems about new ways to manage the complex issues that arise when trying to optimize pin assignments for both FPGAs and PCBs. (Cadence) Improving Software Development Productivity With Virtual Platforms (CHALK TALK) Are your SoC and embedded design projects increasingly dominated by software development schedules? Join Amelia Dalton as she talks with Frank Schirrmeister of Synopsys about ways to improve software development productivity using virtual platforms. (Synopsys) Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints (WHITE PAPER) Electronic systems designers use FPGAs for their prototype implementations, taking advantage of the devices' reprogrammability to validate hardware and software. Once the design is ready for volume production, designers are finding that certain types of ASICs—specifically, ASICs with a silicon platform and toolset that enable concurrent design with the FPGA, using identical I/Os, memory resources, and IP—help them meet power, performance, and cost targets. (Altera) Confirma™: The Next Era Of Prototyping (CHALK TALK) Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys) Catapult C Synthesis Designing a JPEG Compression Engine (CHALK TALK) Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics) Crossing the Gap between Algorithm and Hardware Implementation (CHALK TALK) In this webcast Amelia Dalton will chat with Stuart Clubb of Mentor Graphics about how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. In this webcast, you will learn about modeling techniques for representing bit-accurate arithmetic in C++ using Mentor Graphics' "Algorithmic C" data types. (Mentor Graphics)

Current Feature Articles One Person Making a Difference by Bryon Moyer It's hard to get attention if you're somewhere people aren't looking. And, of course, in the world of technology, the focus is usually on the technology. That's where the innovation tends to be, and, not least important, that's what's patentable. At least if it's hardware, anyway (jury's still somewhat out on software, although apparently it's full steam ahead if you're patenting a living entity… If only Mary Shelley had known…). Even though technology may be sexy, it doesn't guarantee success by itself. Innumerable brilliant, interesting technologies have come and gone, leaving few to remember, and fewer yet to pine, their brief existences. And we all know of superior technologies that succumbed to inferior technologies for reasons having nothing to do with technological merit. In fact, we probably use some on a daily basis, although we may not speak the names out loud for fear that the vanquishers may come and break our kneecaps. Or our computers. Read More Accelerating Exploration Cadence Adds Auto Floorplan Synthesis to Encounter by Bryon Moyer A Cloud-On-A-Chip The Kind of Fun Stuff Intel Gets To Do In The Labs by Bryon Moyer EDA Taking Its Toll by Bryon Moyer Attacking Constraint Complexity Part 2 – E Soft and SystemVerilog Default Constraints by Benjamin Chen, Krishnamoorthy, Srinath Atluri, Nimalan Siva, Alexander Wakefield, and Balamurugan Veluchamy Yet Another Parallel Approach PrimeTime Gets Multi-threading by Bryon Moyer Latest News March 30, 2010 Sondrel Adopts Azuro Clock Tree Synthesis Solution to Deliver Lowest Power Tanner EDA Adds Kelleher Systems as Distributor for Full-flow Analog IC Design Tool Suite D-Tools Enhances Manufacturer Vantage Point (MVP) Program with Legacy Partner, AudioControl SMIC Bases DFM Sign-off Strategy on Mentor Graphics Calibre Platform Cypress Introduces PSoC 3® and PSoC 5 Device Selection Tool To Help Designers Easily Customize the Perfect PSoC Solution Synopsys Galaxy Implementation Platform enables first-pass silicon success on Infineon's 40-nanometer X-GOLD 626 wireless product March 29, 2010 EnSilica launches major new version of its eSi-RISC Development Suite Design Compiler 2010 doubles productivity of synthesis and place and route March 25, 2010 Kilopass First to Offer Logic Non-Volatile Memory (NVM) in TSMC™ 40nm and 45nm Low-Power (LP) Processes March 24, 2010 EMA CircuitSpace 4.0 Allows Flexible Replication and Design Reuse Tanner EDA and Dongbu HiTek Semiconductor Jointly Develop Foundry-certified Process Design Kits (PDKs) for Critical Process Nodes March 23, 2010 ASTER announces the first DfT software to combine Electrical and Mechanical analysis Sidense Participating in IPextreme's Constellations Semiconductor IP Conference Mentor Graphics Calibre LFD Certifications at TSMC Now Include 28nm Process Node with TSMC UDFM Engine New in the Forums I shure hope so I really hope that one day massive analog arrays are feasible. We do not use high frequencies (20-150kHz), so we are the low-frequency category. Having an analog computation engine would be great, as it is inherent real-time. But the amount of filtering w... Posted on 03/25/10 at 3:25 AM by: jast What would you do with 48 cores? Implementing massive parallel algorithms would be the obvious answer. But that is exactly what I would be doing. Working in Sonar research, we often need a massive amount of bandpass filters (no, an STFFT just won't do it), and more operations on the band... Posted on 03/25/10 at 3:20 AM by: jast How much do you really explore? This week we took a look an approach Cadence is providing to allow more floorplan exploration. But floorplanning is just a part of a complex design process that involves lots of tradeoff... Posted on 03/23/10 at 6:37 PM by: bmoyer

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