IC Journal - March 30, 2010

a techfocus media publication :: March 30, 2010

From the Editor Technology programs come and go. Some are successful, some aren't. But the success of some businesses can be determined as much by business model or marketing programs as much as technology. And again, some are successful; some aren't. This week we take a look at one program, notable both for the tenacity of its champion and the staying power of its main protagonist. As yet, it wouldn't be considered notable for its success. Read ahead and see... In January it was Cliff. In February it was Ian. Now, there are just a few days left for YOU to be our March winner of a $500 Amazon.com gift certificate for the best posts on Journal Forums. Thanks as always for reading. We encourage you to share your thoughts in the new easier-to-use comments area right below the articles; don't be shy. Or you can get a lively discussion going on our new FORUMS. Bryon Moyer - Editor, IC Journal        EVENTS & ANNOUNCEMENTS Webinar: Complementing Emulation with Rapid Prototyping In this on-demand webcast Synopsys discusses how FPGA-based rapid prototyping is used as a natural complement to emulation when shortening development time is critical to ASIC and SoC projects. Together, these systems offer designers and verification engineers a highly powerful and productive solution for hardware debug, system integration, system validation and pre-silicon software development to reduce the risk of design re-spins, minimize schedule risk and meet demanding time-to-market needs. Click here to watch IC Journal Forum Competition Win 500 bucks just for being smart! LEMME AT THEM FORUMS! (Click here for competition details) On Demand Billion Gate Emulation with ZeBu-Server (CHALK TALK) Running out of verification capacity? Today's huge designs demand a new solution with dramatically improved speed, capacity, and flexibility. Join Amelia Dalton as she talks with Ron Choi of Eve about the challenges of Billion-Gate emulation. (EvE) Solving Today's Tough FPGA Design Problems (CHALK TALK) Are your FPGAs outgrowing your tool flow? Join Amelia Dalton as she talks with Jeff Garrison of Synopsys about setting up your design tools for today's more demanding FPGAs. (Synopsys) Introducing Synphony High Level Synthesis (CHALK TALK) Having difficulty getting complex algorithms into hardware? Join Amelia Dalton as she chats with Chris Eddington from Synopsys about the latest advances in high-level synthesis - going directly from Matlab into optimized hardware design. (Synopsys) Power Management in an Embedded Multiprocessor Cluster (WHITE PAPER) Coherent microprocessor clusters, having localized instruction and data caches per CPU, require special techniques to maintain consistency between localized cache contents and their common address region. For embedded systems, designers typically apply snoop-based schemes to maintain memory coherence. This scheme introduces ownership attributes of local cache lines, which are posted throughout the cluster upon intent to use or change. (MIPS) ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers (WHITE PAPER) Moore's law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically "break" existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools. (EvE) FPGA - PCB Co-Design Done The Right Way (CHALK TALK) Join Amelia Dalton as she talks with Hemant Shah of Cadence Design Systems about new ways to manage the complex issues that arise when trying to optimize pin assignments for both FPGAs and PCBs. (Cadence) Improving Software Development Productivity With Virtual Platforms (CHALK TALK) Are your SoC and embedded design projects increasingly dominated by software development schedules? Join Amelia Dalton as she talks with Frank Schirrmeister of Synopsys about ways to improve software development productivity using virtual platforms. (Synopsys) Generating Functionally Equivalent FPGAs and ASICs With a Single Set of RTL and Synthesis/Timing Constraints (WHITE PAPER) Electronic systems designers use FPGAs for their prototype implementations, taking advantage of the devices' reprogrammability to validate hardware and software. Once the design is ready for volume production, designers are finding that certain types of ASICs—specifically, ASICs with a silicon platform and toolset that enable concurrent design with the FPGA, using identical I/Os, memory resources, and IP—help them meet power, performance, and cost targets. (Altera) Confirma™: The Next Era Of Prototyping (CHALK TALK) Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys) Catapult C Synthesis Designing a JPEG Compression Engine (CHALK TALK) Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics) Crossing the Gap between Algorithm and Hardware Implementation (CHALK TALK) In this webcast Amelia Dalton will chat with Stuart Clubb of Mentor Graphics about how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. In this webcast, you will learn about modeling techniques for representing bit-accurate arithmetic in C++ using Mentor Graphics' "Algorithmic C" data types. (Mentor Graphics)

Current Feature Articles One Person Making a Difference by Bryon Moyer It's hard to get attention if you're somewhere people aren't looking. And, of course, in the world of technology, the focus is usually on the technology. That's where the innovation tends to be, and, not least important, that's what's patentable. At least if it's hardware, anyway (jury's still somewhat out on software, although apparently it's full steam ahead if you're patenting a living entity… If only Mary Shelley had known…). Even though technology may be sexy, it doesn't guarantee success by itself. Innumerable brilliant, interesting technologies have come and gone, leaving few to remember, and fewer yet to pine, their brief existences. And we all know of superior technologies that succumbed to inferior technologies for reasons having nothing to do with technological merit. In fact, we probably use some on a daily basis, although we may not speak the names out loud for fear that the vanquishers may come and break our kneecaps. Or our computers. Read More Accelerating Exploration Cadence Adds Auto Floorplan Synthesis to Encounter by Bryon Moyer A Cloud-On-A-Chip The Kind of Fun Stuff Intel Gets To Do In The Labs by Bryon Moyer EDA Taking Its Toll by Bryon Moyer Attacking Constraint Complexity Part 2 – E Soft and SystemVerilog Default Constraints by Benjamin Chen, Krishnamoorthy, Srinath Atluri, Nimalan Siva, Alexander Wakefield, and Balamurugan Veluchamy Yet Another Parallel Approach PrimeTime Gets Multi-threading by Bryon Moyer Latest News March 30, 2010 Sondrel Adopts Azuro Clock Tree Synthesis Solution to Deliver Lowest Power Tanner EDA Adds Kelleher Systems as Distributor for Full-flow Analog IC Design Tool Suite D-Tools Enhances Manufacturer Vantage Point (MVP) Program with Legacy Partner, AudioControl SMIC Bases DFM Sign-off Strategy on Mentor Graphics Calibre Platform Cypress Introduces PSoC 3® and PSoC 5 Device Selection Tool To Help Designers Easily Customize the Perfect PSoC Solution Synopsys Galaxy Implementation Platform enables first-pass silicon success on Infineon's 40-nanometer X-GOLD 626 wireless product March 29, 2010 EnSilica launches major new version of its eSi-RISC Development Suite Design Compiler 2010 doubles productivity of synthesis and place and route March 25, 2010 Kilopass First to Offer Logic Non-Volatile Memory (NVM) in TSMC™ 40nm and 45nm Low-Power (LP) Processes March 24, 2010 EMA CircuitSpace 4.0 Allows Flexible Replication and Design Reuse Tanner EDA and Dongbu HiTek Semiconductor Jointly Develop Foundry-certified Process Design Kits (PDKs) for Critical Process Nodes March 23, 2010 ASTER announces the first DfT software to combine Electrical and Mechanical analysis Sidense Participating in IPextreme's Constellations Semiconductor IP Conference Mentor Graphics Calibre LFD Certifications at TSMC Now Include 28nm Process Node with TSMC UDFM Engine New in the Forums I shure hope so I really hope that one day massive analog arrays are feasible. We do not use high frequencies (20-150kHz), so we are the low-frequency category. Having an analog computation engine would be great, as it is inherent real-time. But the amount of filtering w... Posted on 03/25/10 at 3:25 AM by: jast What would you do with 48 cores? Implementing massive parallel algorithms would be the obvious answer. But that is exactly what I would be doing. Working in Sonar research, we often need a massive amount of bandpass filters (no, an STFFT just won't do it), and more operations on the band... Posted on 03/25/10 at 3:20 AM by: jast How much do you really explore? This week we took a look an approach Cadence is providing to allow more floorplan exploration. But floorplanning is just a part of a complex design process that involves lots of tradeoff... Posted on 03/23/10 at 6:37 PM by: bmoyer

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Embedded Technology Journal - March 30, 2010

a techfocus media publication :: March 30, 2010

From the Editor A little sanity check from time to time is a good thing. Here at ETJ Galactic Headquarters we like poll our readers, suppliers, and just the average embedded developer on the street. This week we've got the results of a quick microcontroller survey to see what MCU makers are planning - or not. It's good information to have if you're planning a new project soon. In January it was Cliff. In February it was Ian. Now, there are just a few days left for YOU to be our March winner of a $500 Amazon.com gift certificate for the best posts on Journal Forums. Thanks as always for reading. We encourage you to share your thoughts in the new easier-to-use comments area right below the articles; don't be shy. Or you can get a lively discussion going on our new FORUMS. Jim Turley - Editor, Embedded Technology Journal        EVENTS & ANNOUNCEMENTS Looking Beyond Low Power MCUs As more electronic applications require low power or battery power, energy conservation becomes paramount. Today’s applications must consume little power, and in extreme cases, last for up to 15-20 years, while running from a single battery. To enable applications like these, products with Microchip’s nanoWatt XLP Technology offer the industry’s lowest currents for Sleep, where extreme low power applications spend 90%-99% of their time. Click here to learn more. Embedded Technology Journal Forum Competition Win 500 bucks just for being smart! LEMME AT THEM FORUMS! (Click here for competition details) On Demand Evolving the Coverage-Driven Verification Flow (WHITE PAPER) Achieving functional coverage closure is challenging and time-consuming with today's complex designs. Read how unique coverage-targeting algorithms in intelligent testbench automation tools reduce time to coverage closure by 90%. (Mentor Graphics) Lowering Total System Power Using Xilinx FPGAs (CHALK TALK) In this webcast, Chalk Talk host Amelia Dalton talks with Jameel Hussein of Xilinx about optimizing system-level power with FPGAs, and features and tools that simplify low-power design with Xilinx FPGAs. (Xilinx) Pushing The Envelope in FPGA Design Using PlanAhead (CHALK TALK) Want to have the best FPGA designs on the block? You have to push the technology to stay competitive. Join Amelia Dalton as she talks with Greg Daughtry of Xilinx in this Chalk Talk about pushing the envelope in FPGA design. (Xilinx) EasyPath-6 FPGAs Deliver Lowest Total Product Cost in Six Weeks (CHALK TALK) Confused about FPGA cost reduction? There are easy options for even the most sophisticated FPGAs. Join Amelia Dalton and Shekhar of Xilinx in this Chalk Talk about cost-reducing your Virtex FPGA design with EasyPath. (Xilinx) New in the Forums InVisage Image Sensor Technology I can imagine them being used in high-speed applications. High speed cameras heavily benefit from sensitive sensors, as the exposure time can be reduced, thus reducing motion blur. In our project, we do high speed 3D video captures of flying bats,... Posted on 03/27/10 at 4:08 AM by: jast Dynamic memory allocation on small devices I recently had a discussion with some peers about the use of dynamic memory allocation on small embedded devices (like small Atmel microprocessors). What do you think? Is there a purpose for dynamic memory allocation on these small devices with limited me... Posted on 03/25/10 at 6:08 AM by: jast Looks like I dropped a zero. Of Looks like I dropped a zero. Of course 1.1 microns is equivalent to 1100 nanometers. We'll fix it. Posted on 03/23/10 at 3:16 PM by: Jim Turley "the company now uses a Paleolit "the company now uses a Paleolithic 1.1-micron (110 nm) process" Which is it? 1.1 micron (1100 nm) or 0.11 micron (110 nm)? Posted on 03/23/10 at 2:57 PM by: gabor@alacron.com InVisage Image Sensor Technology Jim Turley took a look at quantum dots and image sensors in his article (click here). Do you think this technology might replace CMOS image sensors? Posted on 03/23/10 at 1:57 PM by: kevin

Current Feature Articles Microcontroller Evolution at an End? by Jim Turley How normal are you? Surveys provide an interesting look at the world and a "sanity check" by comparing our colleagues' responses to our own. "Am I a typical programmer, or am I the only one who…?" Recently I've been beavering away on a survey of microcontroller chip makers, users, and developers. The responses were good, and they give us a peek into what users want, need, and don't want. We also get some hints on what microcontroller makers are planning and what they're not.  Read More Inside-Out Pixels and Quantum Dots by Jim Turley The Embedded World Keeps on Growing by Dick Selwood A Cloud-On-A-Chip The Kind of Fun Stuff Intel Gets To Do In The Labs by Bryon Moyer The Moving Picture Show by Jim Turley Actel's Three-Legged Stool by Jim Turley Microchip Maxes Out Mighty Mites by Jim Turley Latest News March 30, 2010 QuickLogic First to Market Display Controller Solution Supporting 60 fps Content Refresh over MDDI Type 2 New Benchmark Comparison of ITTIA DB SQL and SQLite Kozio Introduces In-System Diagnostics for Texas Instruments OMAP™ 4 Platform Saelig Introduces Rugged Puck Antennas for Indoor/Outdoor Wireless Use Terawins, Inc. Selects MIPS Technologies' Processor IP for Next-Generation Multimedia ICs Atomthreads RTOS Adds STM8 Support Infinite Power Solutions Achieves ISO 9001:2008 Certification NEC Electronics America Expands 8-Bit All Flash Microcontrollers for Industrial, Consumer Electronics Precision Control RF Micro Devices® Features Ember ZigBee® Technology In New Family Of High Performance Front End Modules For Smart Energy Applications Lowest Power, 16-Bit, 80Msps ADC Reduces Noise in Data Conversion Systems March 29, 2010 EnSilica launches major new version of its eSi-RISC Development Suite austriamicrosystems' new battery management data acquisition front-end IC features highest accuracy available MIPS Technologies and Virage Logic Partner to Offer Optimized Embedded Memory IP Triple Output, Buck/Buck/Boost Synchronous DC/DC Controller Targets Automotive Start/Stop Systems March 25, 2010 Digi-Key Corporation Announces Stock on NXP Semiconductor's Energy-Efficient Lighting Solution WD® Introduces 2.5-Inch SATA Hard Drives That Meet Demands for Today's AV/DVR and Surveillance Markets Curtiss-Wright Controls Introduces New Rugged VXS Multi-Channel Data Recorder with Solid State Drives MOST150 Now Allows Safety Critical Applications Curtiss-Wright Controls Doubles Memory on Buffer Memory XMC Card and Passes Rugged Qualification March 24, 2010 Digi-Key Corporation Announces Stock on Molex Mini-Fit H2O™ Series MOST150 Broadens In-car Multimedia ADLINK Reveals ATCA Blade with Dual 6-core Intel® Xeon® Processor L5638 VIA Takes the Jitters Out of Online HD Video

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FPGA Journal - March 30, 2010

a techfocus media publication :: March 30, 2010

From the Editor Spring is the time for re-birth and fresh new ideas. This week, we welcome the month of April with a look at one of those technologies that sounds way too good to be true - four dimensional FPGAs. Our latest feature has the details. In January it was Cliff. In February it was Ian. Now, there are just a few days left for YOU to be our March winner of a $500 Amazon.com gift certificate for the best posts on Journal Forums.  Thanks as always for reading. We encourage you to share your thoughts in the new easier-to-use comments area right below the articles; don't be shy. Or you can get a lively discussion going on our new FORUMS. Kevin Morris, Editor FPGA Journal         On Demand Actel FPGAs for Handheld Portable Solutions (CHALK TALK) With the industry's lowest power and widest range of small packages, it's no wonder Actel IGLOO® FPGAs can be found in the latest handheld portable devices. Actel has been designed into a wide array of handheld devices, including smartphones, eBooks, cameras, medical devices, industrial scanners, military radios, and the list goes on. Actel IGLOO low power FPGAs bring reprogrammability, design security, integration, small form factor, and live-at-power-up operation to handheld portable applications. In this webcast host Amelia Dalton chats with Naseem Aslam about Actel solutions for handheld portable applications. (Actel) Driving Flexibility into Automotive Electronics Design (WHITE PAPER) With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation automotive electronic systems, specialization of traditional microcontrollers no longer makes business sense. Now you can develop an exact microcontroller for a specific application by implementing it into an Altera Cyclone IV FPGA for prototyping and volume production. Verification, software development, and field testing can be done immediately after design or even in parallel. (Altera) Next Generation System Design – Platforms versus Tool-Chains (WHITE PAPER) This paper will enumerate the benefits of a platform-based system design approach. The original electronic design process built by linking tools together has remained largely unchanged for decades (i.e. tool-chains). A layered platform architecture unifies PCB, FPGA and embedded software development into one application. At the foundation is a unified data model that enables numerous data management benefits including versioning and ECO management. Companies switching to a platform based design process are doubling their productivity as compared to traditional tool-chains. (Altium) Easily Support WDR CMOS Image Sensor Processing with Low-Cost FPGAs (VIDEO) High-definition (HD) wide dynamic range (WDR) CMOS image sensors are ideal for applications like video surveillance cameras. And for the underlying technology, FPGAs are optimal because they deliver the high bandwidth these sensors demand. In this 7-minute video, you'll see how an FPGA-based platform easily performs complex image processing to support WDR CMOS image sensors. (Altera) Design Made Easy With Mixed-Signal FPGAs and State of the Art Software Tools (WHITE PAPER) This paper examines the evolution path for FPGAs with embedded processors, and the design tools that support them, and considers whether engineers need to evolve their techniques to accommodate the integrated silicon or whether they can continue to manage their boundaries at the silicon level instead of the board level. New techniques are available in the embedded mixed‐signal FPGA design flow, but do they smooth the adoption of a fully integrated device? Find out by reading the White Paper. (Actel) Targeting and Retargeting Guide for Spartan-6 FPGAs (WHITE PAPER) When targeting or retargeting code from a prior design, some considerations should be made to achieve a quicker and more optimal design when selecting a Spartan®-6 FPGA. This white paper identifies and details the appropriate targeting guidelines and other considerations needed to achieve an improved result for these devices. (Xilinx) Xilinx FPGA Embedded Memory Advantages (WHITE PAPER) The Virtex®-6 and Spartan®-6 architectures feature flexible internal memory resources that can be configured in a variety of different sizes. This white paper details the available features, illustrating the wide array of memory sizes available and shows the trade-off of using different resources to perform memory functions of different sizes. (Xilinx) Actel SmartFusion: Intelligent, Innovative Integration (WHITE PAPER) Actel SmartFusion™ Intelligent Mixed Signal FPGAs – Innovative, Intelligent, Integration. Introducing the only device that integrates a flash FPGA, hard ARM® Cortex™-M3-based microcontroller subsystem (MSS) and programmable analog into a complete, integrated solution. Don't compromise your embedded design. Build the system you want, with all the features you need, on a single-chip solution. Read the White Paper to learn more. (Actel) Simplifying Multi-Rail Power Management for FPGA designers (CHALK TALK) Designing a multi-rail power subsystem? Make it easy, and protect expensive ICs, such as FPGAs. Complex designs call for powerful and sophisticated solutions without compromising ease and speed of design. Join Amelia Dalton as she talks with Dave Clemens of Linear Technology about how you can easily set up all-in-one supervising, sequencing, controlling and monitoring of multiple power supplies. (Linear Technology) Latest News March 30, 2010 QuickLogic First to Market Display Controller Solution Supporting 60 fps Content Refresh over MDDI Type 2 Curtiss-Wright Controls Announces its First OpenVPX/VITA-65 Serial RapidIO® GEN-2 Switch Lowest Power, 16-Bit, 80Msps ADC Reduces Noise in Data Conversion Systems Synopsys Galaxy Implementation Platform enables first-pass silicon success on Infineon's 40-nanometer X-GOLD 626 wireless product March 29, 2010 Pigeon Point Systems Announces IPMC And Carrier IPMC BMR Starter Kits Using SmartFusion Intelligent Mixed Signal FPGAs EnSilica launches major new version of its eSi-RISC Development Suite Pigeon Point Systems Delivers New MMC Management Solution Using SmartFusion Intelligent Mixed Signal FPGAs Altera Rolls Out Production Shipments of Low-Cost, Low-Power Cyclone IV FPGAs Design Compiler 2010 doubles productivity of synthesis and place and route Triple Output, Buck/Buck/Boost Synchronous DC/DC Controller Targets Automotive Start/Stop Systems March 25, 2010 Curtiss-Wright Controls Introduces New Rugged VXS Multi-Channel Data Recorder with Solid State Drives Curtiss-Wright Controls Doubles Memory on Buffer Memory XMC Card and Passes Rugged Qualification March 24, 2010 IAR Systems Supports Actel's New SmartFusion Intelligent Mixed Signal FPGAs Avnet Spartan-6 FPGA DSP Development Kit Jump Starts DSP Designs

Current Feature Articles Dimensional Breakthrough Startup Introduces 4D FPGAs by Kevin Morris Just when we were trying to digest the recent announcements of 3D FPGA devices, along comes a horizon-widening announcement from TesseracTech of their plans for 4D FPGAs. With companies like Tabula and Tier Logic working to gain a process node or two with their newly announced 3D device architectures, TesseracTech is upping the ante - bringing the first four-dimensional chips to the forefront. "We've known that 3D chips were coming for awhile," explains Elliott Henthorn, TesseracTech VP of marketing. "Honestly, we knew that three dimensions would never be enough. Xilinx and Altera can usually level the playing field by keeping a couple of process nodes ahead with their 2D technology, and we believe a fourth dimension is required to sustain a real competitive advantage."  Read More Tabula Gets Real Launches ABAX 3D FPGA Family by Kevin Morris Measuring Safety, an FPGA at a Time by Dick Selwood It's Just Cool Is Smart Fusion an FPGA? Who Cares? by Kevin Morris The Spacetime Continuum Tabula Explains 3D FPGAs by Kevin Morris Cards on the Table Xilinx Announces 28nm Plans by Kevin Morris EVENTS & ANNOUNCEMENTS FPGA Design Methods for Fast Turnaround This white paper provides an in depth look at a variety of techniques to help you speed up your synthesis iterations. Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations. Download now. Bugged by Debugging? Techfocus Media is conducting a survey about the verification and debugging challenges of today’s most advanced FPGAs. After completing the survey, you can register for our prize drawing to win one of five $25 gift certificates to Amazon.com. Click here to complete the survey FPGA Journal Forum Competition Win 500 bucks just for being smart! LEMME AT THEM FORUMS! (Click here for competition details) New in the Forums 4D FPGAs We wrote about four-dimensional FPGAs. (click here) Do you think you'll be using some in the future? We don't. Posted on 03/30/10 at 6:35 PM by: kevin I wanted to comment on a few of I wanted to comment on a few of the questions raised following Kevin's article. . The question of where the states are kept is a very insightful and important one. The second question of where we keep the 8 copies of the LUTs and MUXes is also very inter... Posted on 03/30/10 at 11:57 AM by: Alain Bismuth I got a little suprise in my mailbox today It seems that I have written the last post a bit to eagerly: In my email inbox was an email, stating that a package from the US had arrived at the reception, with the question if I had ordered something in the US. I jumped a meter, and hurried downstairs ... Posted on 03/25/10 at 5:29 PM by: jast Jast - I have to confess we Jast - I have to confess we got a little surprised with the initial demand for the Evaluation Kit. Our distributors had stock on the day of the launch, but quickly ran out. At $99, we should have known the demand could be higher than anticipated. T... Posted on 03/25/10 at 4:37 PM by: Xris A simulation is only as good as the models you use A simulation is only as good as the models you use. Although I like to simulate blocks like state machines, clock dividers, ... The more simple logic blocks that need to behave well, because their performance can really make or break a system. I would nev... Posted on 03/25/10 at 3:12 AM by: jast Actel SmartFusion We only need one/two devices, so the price does not really matter... The Smartfusion evaluation kit is actually exactly what we need, is suits our requirements perfectly. And $99 is ridiculously cheap for research labs I am a bit disappointed though... Posted on 03/25/10 at 3:01 AM by: jast Gabor - SmartFusion was desig Gabor - SmartFusion was designed and is priced to replace an equivalent 32-bit microcontroller and similar FPGA. Pricing is obviously much dependent on the volume purchased and device type/size. If you wish to get precise pricing for your application, ... Posted on 03/24/10 at 7:11 PM by: Xris Actel SmartFusion The first thing I thought when I heard about the device was: Finally!!! I personally love them. I work in the field of biomimetic sonar research, and we often need 2 ADC channels @500kHz, and one DAC channel, 500kHz. This device seems to have both in o... Posted on 03/19/10 at 4:43 AM by: jast

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