  Get an initial look at the industry's first 28-nm high-end FPGA. In our Stratix® V FPGAs, you'll get devices featuring: An industry-record 3.9 billion transistors, One million logic elements, Integrated transceivers with data rates up to 28 Gbps and an abundance of hard intellectual property (IP) blocks. Samples are shipping now. Watch this 3-minute video to see the progress of our silicon checkout process, as well as 14.1-Gbps transceiver performance. (Altera)  Altera's 28-nm devices provide a diversified product portfolio tailored to support a broad spectrum of applications, ranging from low cost and power, to high-end applications. This white paper describes the power and cost advantages of Altera's Stratix® V, Cyclone® V, Arria® V, and HardCopy® V devices. (Altera)   In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package. (Arrow)   This application note describes a parameterizable content-addressable memory (CAM), and is accompanied by a reference design that replaces the CAM core previously delivered through the CORE Generator™ software. The CAM reference design should be used for all new FPGA designs targeting Virtex®-6, Virtex-5, Virtex-4, Spartan®-6, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP FPGAs, and newer architectures. All the features and interfaces included in the reference design are backward compatible with the LogiCORE™ IP CAM v6.1 core. In addition, because the reference design is provided in plain-text VHDL format, the implementation of the function is fully visible, allowing for easy debug and modification of the code. (Xilinx)  Mark Quartermain of Xilinx explains how the next generation of 4G digital cellular standards, Long Term Evolution, represents a significant step forward for wireless operators...and more! (Xilinx)  In a world where attacks on electronic systems can be conducted remotely, security is a vital component of system design. Even systems that do not have to store personal or commercially confidential data now have to be designed with security in mind to prevent their core intellectual property (IP) from being copied and reused illegally. In these examples, we can see the two elements of electronic system security: design security and data security. Increasingly, the two depend on each other. (Microsemi) When high-energy ions present in space strike the substrate of an IC, their impact can cause momentary current/voltage pulses in the IC's circuitry. When these pulses are sufficient to change the data on the circuit, they are referred to collectively as single-event effects (SEEs). (Microsemi)  This is part two of a multi-part white paper series on effectively testing embedded display systems. This function requires a clear understanding of the various interfaces which may exist in the system, and the detailed challenges in testing and debugging them. This paper describes a number of specific techniques for testing a parallel Display Pixel Interface (DPI), which is both the most common and the most physically complex display interconnection (Kozio) Embedded processors are becoming dramatically more sophisticated, and in many cases that sophistication includes a variety of user interface devices. View this video to see how the kDiagnostics environment has been enhanced to support these user interfaces. (Kozio)  In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system. (Altium) |   Power has always been a design consideration. Traditionally, though, a lower priority has been assigned to power than to most other variables (speed/performance, cost, time-to-market, risk, etc.). In today's marketplace, however, power has become a very important component in the designer's decision making process. There is good reason for this. Power translates to significant system cost. (Lattice) Implementing a high-speed, high-efficiency DDR3 memory controller in a FPGA is a formidable task. Until recently, only a few high-end (read: expensive) FPGAs supported the building blocks needed to interface reliably to high speed DDR3 memory devices. However, a new generation of mid-range FPGAs now provides the building blocks, a high-speed FPGA fabric, clock management resources and the I/O structures needed to implement the next generation DDR3 memory controllers. (Lattice)  With their associated software-development tools, simulation models, and EDA flow scripts, processor and DSP IP blocks affect more than just the hardware design; their influence permeates the entire SOC design project. Here is a list of questions to ask yourself, your team, and any processor IP providers you contact. This list will help you to avoid unhappy IP choices and will help you get exactly what your team needs to develop successful SOC designs on time, within budget, and with minimal hassle. (Tensilica) There are plenty of really good, proven processor cores on the market today. But if you have more than simple control tasks, perhaps you've considered using a processor that you can customize. We'll give you 10 good reasons why you should consider customizing your core in your next SOC design. (Tensilica) |
